74HC595PW

The 74HC595PW is a 8-bit serial-in/serial or parallel-out Shift Register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A low on MR will reset the shift register. Data is shifted on the low-to-high transitions of the SHCP input. The data in the shift register is transferred to the storage register on a low-to-high transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the OE is low. A high on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes.

• Shift register with direct clear
• 100MHz Typical shift out frequency
• CMOS Input level
• Complies with JEDEC standard No. 7A