74HC165D

The 74HC165D is a 8-bit serial or parallel-in/serial-out Shift Register features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is low the data from D0 to D7 is loaded into the shift register asynchronously. When PL is high data enters the register serially at DS. When the clock enable input (CE) is low data is shifted on the low-to-high transitions of the CP input. A high on CE will disable the CP input. Inputs include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

• Asynchronous 8-bit parallel load
• Synchronous serial input
• CMOS Input level
• Complies with JEDEC standard No. 7A